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| LIS331DL MEMS motion sensor 3-axis - 2g/8g smart digital output "nano" accelerometer Features 2.16 V to 3.6 V supply voltage 1.8 V compatible IOs <1 mW power consumption 2g / 8g dynamically selectable full-scale I2C/SPI digital output interface Programmable interrupt generator Embedded click and double click recognition Embedded free-fall and motion detection Embedded high pass filter Embedded self test 10000 g high shock survivability ECOPACK(R) RoHS (see Section 9) and "Green" compliant process developed by ST to produce inertial sensors and actuators in silicon. The IC interface is manufactured using a CMOS process that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics. The LIS331DL has dynamically user selectable full scales of 2g/8g and it is capable of measuring accelerations with an output data rate of 100 Hz or 400 Hz. A self-test capability allows the user to check the functioning of the sensor in the final application. The device may be configured to generate inertial wake-up/free-fall interrupt signals when a programmable acceleration threshold is crossed at least in one of the three axes. Thresholds and timing of interrupt generators are programmable by the end user on the fly. The LIS331DL is available in plastic Land Grid Array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 C to +85 C. LGA 16 (3x3x1 mm) Applications Free-Fall detection Motion activated functions Gaming and virtual reality input devices Vibration monitoring and compensation Description The LIS331DL, belonging to the "nano" family of ST motion sensors, is the smallest consumer lowpower three axes linear accelerometer. The device features digital I2C/SPI serial interface standard output and smart embedded functions. The sensing element, capable of detecting the acceleration, is manufactured using a dedicated Table 1. Device summary Temp range [C] -40 to +85 -40 to +85 Order code LIS331DL LIS331DLTR Package LGA LGA Packing Tray Tape and reel April 2008 Rev 3 1/42 www.st.com 42 Contents LIS331DL Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 2.3.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C - Inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.1 2.5.2 2.5.3 2.5.4 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 3.2 3.3 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 5.2.2 5.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/42 LIS331DL Contents 6 7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CTRL_REG3 [interrupt CTRL register] (22h) . . . . . . . . . . . . . . . . . . . . . . 26 HP_FILTER_RESET (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_X (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_Y (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OUT_Z (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FF_WU_CFG_1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FF_WU_SRC_1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_THS_1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_DURATION_1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_CFG_2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_SRC_2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_THS_2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_DURATION_2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CLICK_THSY_X (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CLICK_THSZ (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CLICK_TimeLimit (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CLICK_Latency (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CLICK_Window (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1 8.2 8.3 Mechanical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Mechanical characteristics derived from measurement in the -40 C to +85 C temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Electrical characteristics at 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3/42 Contents LIS331DL 9 10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/42 LIS331DL List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C slave timing diagram (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LIS331DL electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read & write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 X axis Zero-g level at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 X axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Y axis Zero-g level at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Y axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Z axis Zero-g level at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Z axis Sensitivity at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 X axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 X axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Y axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Y axis Sensitivity change vs. temperature at 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Z axis Zero-g level change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Z axis Sensitivity change vs. temperature at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current consumption in normal mode at 2.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LGA 16: Mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5/42 List of tables LIS331DL List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical characteristics @ Vdd=2.5 V, T= 25 C unless otherwise noted . . . . . . . . . . . . 7 Electrical characteristics @ Vdd=2.5 V, T= 25 C unless otherwise noted. . . . . . . . . . . . . . 8 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when Master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when Master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transfer when Master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 17 Transfer when Master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 17 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High pass filter cut-off frequency configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Signal on INT1(2) pad control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OUT_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OUT_Y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OUT_Z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FF_WU_CFG_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FF_WU_CFG_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FF_WU_SRC_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FF_WU_SRC_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FF_WU_THS_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FF_WU_THS_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FF_WU_DURATION_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_DURATION_1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_CFG_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_CFG_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FF_WU_SRC_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_SRC_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_THS_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_THS_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FF_WU_DURATION_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FF_WU_DURATION_2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6/42 LIS331DL Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. List of tables CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLICK_THSY_X register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLICK_THSY_X description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CLICK_THSZ register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CLICK_THSZ description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CLICK_TimeLimit register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CLICK_Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CLICK_Window register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7/42 Block diagram and pin description LIS331DL 1 1.1 Block diagram and pin description Block diagram Figure 1. Block diagram X+ Y+ Z+ CHARGE AMPLIFIER MUX A/D CONVERTER I2C CONTROL LOGIC SPI CS SCL/SPC SDA/SDO/SDI SDO a ZYX- SELF TEST REFERENCE TRIMMING CIRCUITS CONTROL LOGIC CLOCK & INT 1 INT 2 INTERRUPT GEN. 1.2 Pin description Figure 2. Pin connection Z X 1 13 1 Y (TOP VIEW) 9 5 DIRECTION OF THE DETECTABLE ACCELERATIONS (BOTTOM VIEW) 8/42 LIS331DL Table 2. Pin# 1 2 3 4 5 6 Block diagram and pin description Pin description Name Vdd_IO NC NC SCL SPC GND SDA SDI SDO SDO SA0 CS INT 2 Reserved INT 1 GND GND Vdd Reserved GND Power supply for I/O pins Internally Not Connected Internally Not Connected I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) 0V supply I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO) I2C less significant bit of the device address (SA0) SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Inertial interrupt 2 Connect to GND Inertial interrupt 1 0V supply 0V supply Power supply Connect to Vdd 0V supply Function 7 8 9 10 11 12 13 14 15 16 9/42 Mechanical and electrical specifications LIS331DL 2 2.1 Table 3. Symbol FS Mechanical and electrical specifications Mechanical characteristics Mechanical characteristics @ Vdd=2.5 V, T= 25 C unless otherwise noted(1) Parameter Measurement range(3) Test conditions FS bit set to 0 FS bit set to 1 FS bit set to 0 FS bit set to 1 FS bit set to 0 FS bit set to 0 FS bit set to 1 Max delta from 25 C Best fit straight line FS bit set to 0 STP bit used X axis Vst Self test output change(6),(7),(8) FS bit set to 0 STP bit used Y axis FS bit set to 0 STP bit used Z axis BW Top Wh System bandwidth(9) Operating temperature range Product weight -40 20 -3 Min. 2.0 8.0 16.2 64.8 Typ.(2) 2.3 9.2 18 72 0.01 40 60 0.5 0.5 -19 -32 19.8 79.2 Max. Unit g So TCSo TyOff TCOff NL Sensitivity Sensitivity change vs temperature Typical zero-g level offset accuracy(4),(5) Zero-g level change vs temperature Non linearity mg/digit %/C mg mg mg/C % FS LSb 3 19 32 LSb -3 -19 ODR/2 -32 LSb Hz +85 C mgram 1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. 2. Typical specifications are not guaranteed 3. Verified by wafer level test and measurement of initial offset and sensitivity 4. Typical zero-g level offset value after MSL3 preconditioning 5. Offset can be eliminated by enabling the built-in high pass filter 6. If STM bit is used values change in sign for all axes 7. Self Test output changes with the power supply. "Self test output change" is defined as OUTPUT[LSb](Self-test bit on CTRL_REG1=1) -OUTPUT[LSb](Self-test bit on CTRL_REG1=0). 1LSb=4.6g/256 at 8bit representation, 2.3 g Full-Scale 8. Output data reach 99% of final value after 3/ODR when enabling Self-Test mode due to device filtering 9. ODR is output data rate. Refer to Table 4 for specifications 10/42 LIS331DL Mechanical and electrical specifications 2.2 Table 4. Symbol Vdd Vdd_IO Idd IddPdn VIH VIL VOH VOL ODR BW Ton Top Electrical characteristics Electrical characteristics @ Vdd=2.5 V, T= 25 C unless otherwise noted(1) Parameter Supply voltage I/O pins supply voltage(3) Supply current Current consumption in power-down mode Digital high level input voltage Digital low level input voltage High level output voltage Low level output voltage DR=0 Output data rate DR=1 System bandwidth(4) Turn-on time (5) Test conditions Min. 2.16 1.71 Typ.(2) 2.5 Max. 3.6 Vdd+0.1 Unit V V mA A V ODR=100 Hz 0.3 1 0.8*Vdd_IO 0.4 5 0.2*Vdd_IO 0.9*Vdd_IO 0.1*Vdd_IO 100 V V V Hz 400 ODR/2 3/ODR -40 +85 Hz s Operating temperature range C 1. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V. 2. Typical specification are not guaranteed 3. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Filter cut-off frequency 5. Time to obtain valid data after exiting Power-Down mode 11/42 Mechanical and electrical specifications LIS331DL 2.3 2.3.1 Communication interface characteristics SPI - serial peripheral interface Subject to general operating conditions for Vdd and top. Table 5. Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 6 50 5 8 5 15 50 ns SPI slave timing values Value(1) Parameter Min 100 10 Max ns MHz Unit 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3. SPI slave timing diagram (2) CS (3) (3) tsu(CS) tc(SPC) th(CS) (3) SPC (3) tsu(SI) th(SI) MSB IN LSB IN (3) SDI (3) tv(SO) th(SO) LSB OUT tdis(SO) (3) SDO (3) MSB OUT 2. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both Input and Output port 3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors 12/42 LIS331DL Mechanical and electrical specifications 2.3.2 I2C - Inter IC control interface Subject to general operating conditions for Vdd and top. Table 6. I2C slave timing values I2C Standard mode(1) I2C Fast mode (1) Unit Min Max 100 Min 0 1.3 s SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 4 4.7 4 4.7 4.0 250 0(2) 3.45 1000 300 0.6 100 0(2) 20 + 0.1Cb (3) 20 + 0.1Cb (3) 0.6 0.6 s 0.6 1.3 0.9 300 ns 300 ns s Max 400 KHz 0 4.7 Parameter SCL clock frequency SCL clock low time Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(ST) tsu(SR) tsu(SP) tw(SP:SR) 1. Data based on standard I2C protocol requirement, not tested in production 2. A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL 3. Cb = total capacitance of one bus line, in pF Figure 4. I2C slave timing diagram (4) REPEATED START START tsu(SR) SDA tw(SP:SR) START tf(SDA) tr(SDA) tsu(SDA) th(SDA) tsu(SP) STOP SCL th(ST) tw(SCLL) tw(SCLH) tr(SCL) tf(SCL) 4. Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both ports 13/42 Mechanical and electrical specifications LIS331DL 2.4 Absolute maximum ratings Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Symbol Vdd Vdd_IO Vin Supply voltage I/O pins Supply voltage Input voltage on any control pin (CS, SCL/SPC, SDA/SDI/SDO) Acceleration (any axis, powered, Vdd=2.5 V) 10000 g for 0.1 ms 3000 g for 0.5 ms AUNP TOP TSTG Acceleration (any axis, unpowered) 10000 g for 0.1 ms Operating temperature range Storage temperature range -40 to +85 -40 to +125 4 (HBM) ESD Electrostatic discharge protection 1.5 (CDM) 200 (MM) C C kV kV V Absolute maximum ratings Ratings Maximum value -0.3 to 6 -0.3 to 6 -0.3 to Vdd_IO +0.3 3000 g for 0.5 ms Unit V V V APOW Note: Supply voltage on any pin should never exceed 6.0 V This is a mechanical shock sensitive device, improper handling can cause permanent damages to the part This is an ESD sensitive device, improper handling can cause permanent damages to the part 14/42 LIS331DL Mechanical and electrical specifications 2.5 2.5.1 Terminology Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, 1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also over time. The Sensitivity Tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 Zero-g level Zero-g level Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g in X axis and 0 g in Y axis whereas the Z axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see "Zero-g level change vs. temperature". The Zero-g level tolerance (TyOff) describes the Standard Deviation of the range of Zero-g levels of a population of sensors. 2.5.3 Self test Self Test allows to check the sensor functionality without moving it. The self test function is off when the self-test bit of CTRL_REG1 (control register 1) is programmed to `0`. When the self-test bit of ctrl_reg1 is programmed to `1` an actuation force is applied to the sensor, simulating a definite input acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity. When Self Test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. If the output signals change within the amplitude specified inside Table 3, then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 2.5.4 Click and double click recognition The click and double click recognition functions help to create man-machine interface with little software overload. The device can be configured to output an interrupt signal on dedicated pin when tapped in any direction. If the sensor is exposed to a single input stimulus it generates an interrupt request on inertial interrupt pins (INT1 and/or INT2). A more advanced feature allows to generate an interrupt request when a "double click" stimulus is applied. A programmable time between the two events allows a flexible adaption to the application requirements. Mouse-button like application, like clicks and double clicks, can be implemented. This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli. 15/42 Functionality LIS331DL 3 Functionality The LIS331DL is a nano, low-power, digital output 3-axis linear accelerometer packaged in an LGA package. The complete device includes a sensing element and an IC interface able to take the information from the sensing element and to provide a signal to the external world through an I2C/SPI serial interface. 3.1 Sensing element A proprietary process is used to create a surface micro-machined accelerometer. The technology allows to carry out suspended silicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. To be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. When an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. At steady state the nominal value of the capacitors are few pF and when an acceleration is applied the maximum variation of the capacitive load is in the fF range. 3.2 IC interface The complete measurement chain is composed by a low-noise capacitive amplifier which converts the capacitive unbalancing of the MEMS sensor into an analog voltage that is finally available to the user by an analog-to-digital converter. The acceleration data may be accessed through an I2C/SPI interface thus making the device particularly suitable for direct interfacing with a microcontroller. The LIS331DL features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The LIS331DL may also be configured to generate an inertial Wake-Up and Free-Fall interrupt signal accordingly to a programmed acceleration event along the enabled axes. Both Free-Fall and Wake-Up can be available simultaneously on two different pins. 3.3 Factory calibration The IC interface is factory calibrated for sensitivity (So) and Zero-g level (TyOff). The trimming values are stored inside the device in a non volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the normal operation. This allows to use the device without further calibration. 16/42 LIS331DL Application hints 4 Application hints Figure 5. LIS331DL electrical connection Vdd 10F 1 Vdd_IO 13 TOP VIEW 100nF INT 1 5 SDA/SDI/SDO 9 INT 2 SCL/SPC SDO/SA0 GND Digital signal from/to signal controller.Signal's levels are defined by proper selection of Vdd_IO The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 F Al) should be placed as near as possible to the pin 14 of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO without blocking the communication bus, in this condition the measurement chain is powered off. The functionality of the device and the measured acceleration data is selectable and accessible through the I2C/SPI interface.When using the I2C, CS must be tied high. The functions, the threshold and the timing of the two interrupt pins (INT 1 and INT 2) can be completely programmed by the user through the I2C/SPI interface. 4.1 Soldering information The LGA package is compliant with the ECOPACK(R), RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020C. Leave "Pin 1 Indicator" unconnected during soldering. Land pattern and soldering recommendation are available at www.st.com/mems. CS 17/42 Digital interfaces LIS331DL 5 Digital interfaces The registers embedded inside the LIS331DL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be tied high (i.e connected to Vdd_IO). Table 8. Serial interface pin description Pin description SPI enable I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO) I2C less significant bit of the device address (SA0) Pin name CS SCL/SPC SDA/SDI/SDO SDO/SA0 5.1 I2C serial interface The LIS331DL I2C is a bus slave. The I2C is employed to write data into registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 9. Term Transmitter Receiver Master Slave Serial interface pin description Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS331DL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with the normal mode. 18/42 LIS331DL Digital interfaces 5.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS331DL is 001110xb. SDO/SA0 pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is `1' (address 0011101b) else if SDO pad is connected to ground LSb value is `0' (address 0011100b). This solution permits to connect and address two different accelerometers to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LIS331DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was `1' (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is `0' (Write) the Master will transmit to the slave with direction unchanged. Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns SAD[6:1] 001110 001110 001110 001110 SAD[0] = SDO/SA0 0 0 1 1 R/W 1 0 1 0 SAD+R/W 00111001 (39h) 00111000 (38h) 00111011 (3Bh) 00111010 (3Ah) Command Read Write Read Write Table 11. Master Slave Transfer when Master is writing one byte to slave ST SAD + W SAK SUB SAK DATA SAK SP Table 12. Master Slave Transfer when Master is writing multiple bytes to slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP 19/42 Digital interfaces Table 13. Master Slave ST LIS331DL Transfer when Master is receiving (reading) one byte of data from slave SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP Table 14. Master Slave Transfer when Master is receiving (reading) multiple bytes of data from slave ST SAD+W SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn't acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read. In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS331DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. Figure 6. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Read & write protocol SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the Serial Port Enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the Serial Port Clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the Serial Port Data Input and Output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. 20/42 LIS331DL Digital interfaces Both the Read Register and Write Register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block. The function and the behavior of SDI and SDO remain unchanged. 5.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reading. 21/42 Digital interfaces Figure 8. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 LIS331DL Multiple bytes SPI read protocol (2 bytes example) SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 5.2.2 SPI write Figure 9. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SPI write protocol The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writing. Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 22/42 LIS331DL Digital interfaces 5.2.3 SPI read in 3-wires mode 3-wires mode is entered by setting to 1 bit SIM (SPI Serial Interface Mode selection) in CTRL_REG2. Figure 11. SPI read protocol in 3-wires mode CS SPC SDI/O RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). Multiple read command is also available in 3-wires mode. 23/42 Register mapping LIS331DL 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 15. Register address map Register address Name Type Hex Binary Reserved 000 1111 00111011 Dummy register Reserved 010 0000 00000111 010 0001 00000000 010 0010 00000000 010 0011 dummy Dummy register Reserved 010 0111 00000000 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 output Reserved 011 0000 00000000 011 0001 00000000 011 0010 00000000 011 0011 00000000 011 0100 00000000 011 0101 00000000 011 0110 00000000 011 0111 00000000 011 1000 00000000 011 1001 00000000 Not Used 011 1011 00000000 output Not Used output Not Used Not Used 00-0E r 0F 10-1F rw rw rw r 20 21 22 23 24-26 r r r r r r r 27 28 29 2A 2B 2C 2D 2E-2F rw r rw rw rw r rw rw rw r 30 31 32 33 34 35 36 37 38 39 3A rw 3B Default Comment Reserved (do not modify) WHO_AM_I Reserved (do not modify) CTRL_REG1 CTRL_REG2 CTRL_REG3 HP_FILTER_RESET Reserved (do not modify) STATUS_REG -OUT_X -OUT_Y -OUT_Z Reserved (do not modify) FF_WU_CFG_1 FF_WU_SRC_1(ack1) FF_WU_THS_1 FF_WU_DURATION_1 FF_WU_CFG_2 FF_WU_SRC_2 (ack2) FF_WU_THS_2 FF_WU_DURATION_2 CLICK_CFG CLICK_SRC (ack) -CLICK_THSY_X 24/42 LIS331DL Table 15. Register address map (continued) Register address Name CLICK_THSZ CLICK_TimeLimit CLICK_Latency CLICK_Window Type Hex rw rw rw rw 3C 3D 3E 3F Binary 011 1100 00000000 011 1101 00000000 011 1110 00000000 011 1111 00000000 Default Register mapping Comment Registers marked as "Reserved" must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up. 25/42 Register description LIS331DL 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 WHO_AM_I (0Fh) Table 16. 0 WHO_AM_I register 0 1 1 1 0 1 1 Device identification register. This register contains the device identifier that for LIS331DL is set to 3Bh. 7.2 CTRL_REG1 (20h) Table 17. DR CTRL_REG1 register PD FS STP STM Zen Yen Xen Table 18. DR PD FS STP, STM Zen Yen Xen CTRL_REG1 description Data rate selection. Default value: 0 (0: 100 Hz output data rate; 1: 400 Hz output data rate) Power Down Control. Default value: 0 (0: power down mode; 1: active mode) Full Scale selection. Default value: 0 (refer to Table 3 for typical full scale values) Self Test Enable. Default value: 0 (0: normal mode; 1: self test P, M enabled) Z axis enable. Default value: 1 (0: Z axis disabled; 1: Z axis enabled) Y axis enable. Default value: 1 (0: Y axis disabled; 1: Y axis enabled) X axis enable. Default value: 1 (0: X axis disabled; 1: X axis enabled) DR bit allows to select the data rate at which acceleration samples are produced. The default value is 0 which corresponds to a data-rate of 100 Hz. By changing the content of DR to "1" the selected data-rate will be set equal to 400 Hz. PD bit allows to turn the device out of power-down mode. The device is in power-down mode when PD= `0' (default value after boot). The device is in normal mode when PD is set to `1'. STP, STM bits are used to activate the self test function. When the bit is set to one, an output change will occur to the device outputs (refer to Table 3 and 4 for specifications) thus allowing to check the functionality of the whole measurement chain. 26/42 LIS331DL Register description Zen bit enables the generation of Data Ready signal for Z-axis measurement channel when set to 1. The default value is 1. Yen bit enables the generation of Data Ready signal for Y-axis measurement channel when set to 1. The default value is 1. Xen bit enables the generation of Data Ready signal for X-axis measurement channel when set to 1. The default value is 1. 7.3 CTRL_REG2 (21h) Table 19. SIM CTRL_REG2 register BOOT 0(1) FDS HP FF_WU2 HP FF_WU1 HPcoeff2 HPcoeff1 1. Bit to be kept to "0" for correct device functionality Table 20. SIM BOOT FDS HP FF_WU2 HP FF_WU1 HPcoeff2 HPcoeff1 CTRL_REG2 description SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) Filtered Data Selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) High Pass filter enabled for Free-Fall/WakeUp # 2. Default value: 0 (0: filter bypassed; 1: filter enabled) High Pass filter enabled for Free-Fall/Wake-Up #1. Default value: 0 (0: filter bypassed; 1: filter enabled) High pass filter cut-off frequency configuration. Default value: 00 (See Table 21) SIM bit selects the SPI Serial Interface Mode. When SIM is `0' (default value) the 4-wire interface mode is selected. The data coming from the device are sent to SDO pad. In 3-wire interface mode output data are sent to SDA_SDI pad. BOOT bit is used to refresh the content of internal registers stored in the flash memory block. At the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. If for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. When BOOT bit is set to `1' the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. These values are factory trimmed and they are different for every accelerometer. They permit a good behavior of the device and normally they have not to be changed. At the end of the boot process the BOOT bit is set again to `0'. FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor HPcoeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft. 27/42 Register description Table 21. High pass filter cut-off frequency configuration ft (Hz) (ODR=100 Hz) 2 1 0.5 0.25 ft (Hz) (ODR=400 Hz) 8 4 2 1 LIS331DL HPcoeff2,1 00 01 10 11 7.4 CTRL_REG3 [interrupt CTRL register] (22h) Table 22. IHL CTRL_REG3 register PP_OD I2_CFG2 I2_CFG1 I2_CFG0 I1_CFG2 I1_CFG1 I1_CFG0 Table 23. IHL PP_OD I2_CFG2 I2_CFG1 I2_CFG0 I1_CFG2 I1_CFG1 I1_CFG0 CTRL_REG3 description Interrupt active high, low. Default value 0. (0: active high; 1: active low) Push-pull/Open Drain selection on interrupt pad. Default value 0. (0: push-pull; 1: open drain) Data signal on INT2 pad control bits. Default value 000. (see table below) Data signal on INT1 pad control bits. Default value 000. (see table below) Table 24. Data Signal on INT1(2) pad control bits I1(2)_CFG1 0 0 1 1 0 1 I1(2)_CFG0 0 1 0 1 0 1 INT 1(2) Pad GND FF_WU_1 FF_WU_2 FF_WU_1 OR FF_WU_2 Data ready Click interrupt I1(2)_CFG2 0 0 0 0 1 1 7.5 HP_FILTER_RESET (23h) Dummy register. Reading at this address zeroes instantaneously the content of the internal high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0 g. This allows to overcome the settling time of the high pass filter. 28/42 LIS331DL Register description 7.6 STATUS_REG (27h) Table 25. ZYXOR STATUS_REG register ZOR YOR XOR ZYXDA ZDA YDA XDA Table 26. ZYXOR STATUS_REG description X, Y, Z axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) Z axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the Y-axis has overwritten the previous one) X axis Data Overrun. Default value: 0 (0: no overrun has occurred; 1: a new data for the X-axis has overwritten the previous one) X, Y and Z axis new Data Available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z axis new Data Available. Default value: 0 (0: a new data for the Z-axis is not yet available; 1: a new data for the Z-axis is available) Y axis new Data Available. Default value: 0 (0: a new data for the Y-axis is not yet available; 1: a new data for the Y-axis is available) X axis new Data Available. Default value: 0 (0: a new data for the X-axis is not yet available; 1: a new data for the X-axis is available) ZOR YOR XOR ZYXDA ZDA YDA XDA 7.7 OUT_X (29h) Table 27. XD7 OUT_X register XD6 XD5 XD4 XD3 XD2 XD1 XD0 X axis output data expressed as 2's complement number. 7.8 OUT_Y (2Bh) Table 28. YD7 OUT_Y register YD6 YD5 YD4 YD3 YD2 YD1 YD0 Y axis output data expressed as 2's complement number. 29/42 Register description LIS331DL 7.9 OUT_Z (2Dh) Table 29. ZD7 OUT_Z register ZD6 ZD5 ZD4 ZD3 ZD2 ZD1 ZD0 Z axis output data expressed as 2's complement number. 7.10 FF_WU_CFG_1 (30h) Table 30. AOI FF_WU_CFG_1 register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 31. AOI FF_WU_CFG_1 description And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC_1 reg with the FF_WU_SRC_1 reg cleared by reading FF_WU_SRC_1 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) LIR ZHIE ZLIE YHIE YLIE XHIE XLIE 30/42 LIS331DL Register description 7.11 FF_WU_SRC_1 (31h) Table 32. -- FF_WU_SRC_1 register IA ZH ZL YH YL XH XL Table 33. IA ZH ZL YH YL XH XL FF_WU_SRC_1 description Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z High. Default value: 0 (0: no interrupt, 1: Z High event has occurred) Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) Y High. Default value: 0 (0: no interrupt, 1: Y High event has occurred) Y Low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred) X High. Default value: 0 (0: no interrupt, 1: X High event has occurred) X Low. Default value: 0 (0: no interrupt, 1: X Low event has occurred) Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was chosen. 7.12 FF_WU_THS_1 (32h) Table 34. DCRM FF_WU_THS_1 register THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 35. DCRM FF_WU_THS_1 description Resetting mode selection. Default value: 0 (0: counter reset; 1: counter decremented) Free-fall / wake-up Threshold: default value: 000 0000 THS6, THS0 Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration counter is decremented. 31/42 Register description LIS331DL 7.13 FF_WU_DURATION_1 (33h) Table 36. D7 FF_WU_DURATION_1 register D6 D5 D4 D3 D2 D1 D0 Table 37. D7-D0 FF_WU_DURATION_1 description Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400 Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100 Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified 7.14 FF_WU_CFG_2 (34h) Table 38. AOI FF_WU_CFG_2 register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 39. AOI LIR FF_WU_CFG_2 description And/Or combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC_2 reg with the FF_WU_SRC_2 reg cleared by reading FF_WU_SRC_2 reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on Z High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X High event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X Low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) ZHIE ZLIE YHIE YLIE XHIE XLIE 32/42 LIS331DL Register description 7.15 FF_WU_SRC_2 (35h) Table 40. -- FF_WU_SRC_2 register IA ZH ZL YH YL XH XL Table 41. IA FF_WU_SRC_2 description Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) Z High. Default value: 0 (0: no interrupt; 1: Z High event has occurred) ZH ZL YH YL XH XL Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) Y High. Default value: 0 (0: no interrupt; 1: Y High event has occurred) Y Low. Default value: 0 (0: no interrupt; 1: Y Low event has occurred) X High. Default value: 0 (0: no interrupt; 1: X High event has occurred) X Low. Default value: 0 (0: no interrupt; 1: X Low event has occurred) Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_2 register and the FF_WU_2 interrupt and allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was chosen. 7.16 FF_WU_THS_2 (36h) Table 42. DCRM FF_WU_THS_2 register THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 43. DCRM THS6, THS0 FF_WU_THS_2 description Resetting mode selection. Default value: 0 (0: counter reset; 1: counter decremented) Free-fall / wake-up Threshold. Default value: 000 0000 Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration counter is decremented. 33/42 Register description LIS331DL 7.17 FF_WU_DURATION_2 (37h) Table 44. D7 FF_WU_DURATION_2 register D6 D5 D4 D3 D2 D1 D0 Table 45. D7-D0 FF_WU_DURATION_2 description Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400 Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100 Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified. 7.18 CLICK_CFG (38h) Table 46. - CLICK_CFG register LIR Double_Z Single_Z Double_Y Single_Y Double_X Single_X Table 47. LIR CLICK_CFG description Latch Interrupt request into CLICK_SRC reg with the CLICK_SRC reg refreshed by reading CLICK_SRC reg. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Enable interrupt generation on double click event on Z axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on Z axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on double click event on Y axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on Y axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on double click event on X axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on single click event on X axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Double_Z Single_Z Double_Y Single_Y Double_X Single_X Table 48 shows all the possible configurations for Click and Double Click recognition. 34/42 LIS331DL Table 48. Click interrupt configurations Single_Z / Y / X 0 1 0 1 Register description Double_Z / Y / X 0 0 1 1 Click output 0 Single Double Single OR Double 7.19 CLICK_SRC (39h) Table 49. -- CLICK_SRC register IA Double_Z Single_Z Double_Y Single_Y Double_X Single_X Table 50. IA CLICK_SRC description Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) Double click on Z axis event. Default value: 0 (0: no interrupt; 1: Double Z event has occurred) Single click on Z axis event. Default value: 0 (0: no interrupt; 1: Single Z event has occurred) Double click on Y axis event. Default value: 0 (0: no interrupt; 1: Double Y event has occurred) Single click on Y axis event.Default value: 0 (0: no interrupt; 1: Single Y event has occurred) Double click on X axis event. Default value: 0 (0: no interrupt; 1: Double X event has occurred) Single click on X axis event. Default value: 0 (0: no interrupt; 1: Single X event has occurred) Double_Z Single_Z Double_Y Single_Y Double_X Single_X 7.20 CLICK_THSY_X (3Bh) Table 51. THSy3 CLICK_THSY_X register THSy2 THSy1 THSy0 THSx3 THSx2 THSx1 THSx0 Table 52. CLICK_THSY_X description THSy3, THSy0 Click Threshold on Y axis. Default value: 0000 THSx3, THSx0 Click Threshold on X axis. Default value: 0000 From 0.5 g (0001) to 7.5 g (1111) with step of 0.5 g. 35/42 Register description LIS331DL 7.21 CLICK_THSZ (3Ch) Table 53. -- CLICK_THSZ register ---THSz3 THSz2 THSz1 THSz0 Table 54. CLICK_THSZ description THSz3, THSz0 Click Threshold on Z axis. Default value: 0000 From 0.5 g (0001) to 7.5 g (1111) with step of 0.5 g. 7.22 CLICK_TimeLimit (3Dh) Table 55. Dur7 CLICK_TimeLimit register Dur6 Dur5 Dur4 Dur3 Dur2 Dur1 Dur0 From 0 to 127.5 msec with step of 0.5 msec, 7.23 CLICK_Latency (3Eh) Table 56. Lat7 CLICK_Latency Lat6 Lat5 Lat4 Lat3 Lat2 Lat1 Lat0 From 0 to 255 msec with step of 1 msec. 7.24 CLICK_Window (3Fh) Table 57. Win7 CLICK_Window register Win6 Win5 Win4 Win3 Win2 Win1 Win0 From 0 to 255 msec with step of 1 msec. 36/42 LIS331DL Typical performance characteristics 8 8.1 Typical performance characteristics Mechanical characteristics at 25 C Figure 13. X axis Sensitivity at 2.5 V 25 Figure 12. X axis Zero-g level at 2.5 V 25 20 20 Percent of parts [%] 15 Percent of parts [%] -100 -50 0 50 Zero-g Level Offset [mg] 100 150 15 10 10 5 5 0 -150 0 16 16.5 17 17.5 18 18.5 Sensitivity [mg/digits] 19 19.5 20 Figure 14. Y axis Zero-g level at 2.5 V 20 18 16 14 Figure 15. Y axis Sensitivity at 2.5 V 20 18 16 14 Percent of parts [%] 12 10 8 6 4 2 0 -150 Percent of parts [%] -100 -50 0 50 Zero-g Level Offset [mg] 100 150 12 10 8 6 4 2 0 16 16.5 17 17.5 18 18.5 Sensitivity [mg/digits] 19 19.5 20 Figure 16. Z axis Zero-g level at 2.5 V 25 Figure 17. Z axis Sensitivity at 2.5 V 25 20 20 Percent of parts [%] 15 Percent of parts [%] -100 -50 0 50 Zero-g Level Offset [mg] 100 150 15 10 10 5 5 0 -150 0 16 16.5 17 17.5 18 18.5 Sensitivity [mg/digits] 19 19.5 20 37/42 Typical performance characteristics LIS331DL 8.2 Mechanical characteristics derived from measurement in the -40 C to +85 C temperature range Figure 19. X axis Sensitivity change vs. temperature at 2.5 V 30 Figure 18. X axis Zero-g level change vs. temperature at 2.5 V 30 25 25 20 Percent of parts [%] Percent of parts [%] 20 15 15 10 10 5 5 0 -4 -3 -2 -1 0 0-g level drift [mg/oC] 1 2 3 4 0 -0.1 -0.05 0 Sensitivity drift [%/oC] 0.05 0.1 0.15 Figure 20. Y axis Zero-g level change vs. temperature at 2.5 V 35 Figure 21. Y axis Sensitivity change vs. temperature at 2.5 V 35 30 30 25 Percent of parts [%] Percent of parts [%] 25 20 20 15 15 10 10 5 5 0 -4 -3 -2 -1 0 0-g level drift [mg/oC] 1 2 3 4 0 -0.1 -0.05 0 Sensitivity drift [%/oC] 0.05 0.1 0.15 Figure 22. Z axis Zero-g level change vs. temperature at 2.5 V 30 Figure 23. Z axis Sensitivity change vs. temperature at 2.5 V 30 25 25 20 Percent of parts [%] Percent of parts [%] 20 15 15 10 10 5 5 0 -4 -3 -2 -1 0 0-g level drift [mg/ C] o 1 2 3 4 0 -0.1 -0.05 0 Sensitivity drift [%/ C] o 0.05 0.1 0.15 38/42 LIS331DL Typical performance characteristics 8.3 Electrical characteristics at 25 C Figure 24. Current consumption in normal mode at 2.5 V 20 18 16 14 Percent of parts [%] 12 10 8 6 4 2 0 200 220 240 260 280 300 320 340 Current consumption [uA] 360 380 400 39/42 Package information LIS331DL 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK(R) is an ST trademark. ECOPACK(R) specifications are available at: www.st.com. Figure 25. LGA 16: Mechanical data and package dimensions Dimensions Ref. A1 A2 A3 D1 E1 L1 L2 N1 N2 M P1 P2 T1 T2 d k 0.290 0.190 0.040 2.850 2.850 0.785 0.200 3.000 3.000 1.000 2.000 0.500 1.000 0.100 0.875 1.275 0.350 0.250 0.150 0.050 mm Min. Typ. Max. 1.000 inch Min. Typ. 0.0309 0.0079 3.150 0.1122 0.1181 0.1240 3.150 0.1122 0.1181 0.1240 1.060 2.060 0.0394 0.0417 0.0787 0.0811 0.0197 0.0394 0.160 0.0016 0.0039 0.0063 0.0344 0.0502 0.410 0.0114 0.0138 0.0161 0.310 0.0075 0.0098 0.0122 0.0059 0.0020 Max. 0.0394 Outline and mechanical data LGA16 (3x3x1.0mm) Land Grid Array Package 7983231 40/42 LIS331DL Revision history 10 Revision history Table 58. Date 28-Sep-2007 21-Jan-2008 Document revision history Revision 1 2 Initial release Updated package specification Figure 25: LGA 16: Mechanical data and package dimensions on page 40. Minor text changes to improve readability. Updated paragraph 2.1: Mechanical characteristics and added section 8: Typical performance characteristics. Updated POA Changes 16-Apr-2008 3 41/42 LIS331DL Please Read Carefully: Information in this document is provided solely in connection with ST products. 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